`timescale 1ns/1ps
module traffic_light_top;
    reg reset,start,clock;
    wire red,yellow,green;

    always # 1 clock = ~clock;
    initial begin
        reset = 0;
        clock = 0;
        start = 0;
        # 2 reset =1;
        # 2 reset =0;
        start =1;
        # 20 start = 0; 
        # 4 $stop;

    end

    traffic_light tf(red,yellow,green,reset,start,clock);
	initial
	begin
    	$dumpfile("test.vcd");
    	$dumpvars(0, tf);
 	end
endmodule

module traffic_light(red,yellow,green,reset,start,clock);
    input reset,start,clock;
    output red,yellow,green;
    reg [2:0] state,next;
    parameter RESET = 3'b000,START = 3'b001,Y = 3'b010,G1 = 3'b011,G2 = 3'b100,G3 = 3'b101,R= 3'b110;
    
    assign red = (state==RESET|state==START|state==R)?1:0;
    assign yellow = (state == Y)?1:0;
    assign green = (state == G1|state == G2|state == G3)?1:0;
    always@(posedge clock or posedge reset )
        if (reset)
            state <= RESET;
    	else
            state <= next;
    always@(*)
        case(state)
            RESET:next = (start)?START:RESET;
            START:next = (reset)?RESET:Y;
            Y:next = (reset)?RESET:G1;
            G1:next = (reset)?RESET:G2;
            G2:next = (reset)?RESET:G3;
            G3:next = (reset)?RESET:R;
            R:next = RESET;
            default:next = RESET;         
        endcase
    
endmodule
